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FPGA Camp is a conference, which brings engineers together and discusses FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories.

We are please to hold first ever Camp in India, so come and join us.

Since its inception in Year 2009, FPGA Camp decided to stay vendor neutral and the only conference to not charge its attendees speakers or vendors any money. Hence the attendance is completely FREE (free like in beer) and so is putting up a booth. Due to the this approach we soon have been coined as an Open Source conference by Industry leaders like Eric Bogatin (here), Colin Warwick (here) & Max Maxfield (here)

Ofcourse we do rely on our completely optional sponsors & volunteers to help us arrange the events, so if you would like to help out, contact us at fpgacamp @fpgcentral.com

Details:

Today's FPGA Ecosystem

Presenters -

Neeraj Varma, Country Manager - Sales, India and Australia/NZ, Xilinx

Responsible for Xilinx Sales in the India, Australia and New Zealand territories. Managing a manufacturer's representative firm, as well as two global distributors for this territory. Neeraj has also worked with CG-CoreEl Programmables, Synplicity, Memec. He holds an Engineering degree in Electronics and MBA.

Gangatharan  Gopal, Country Manager, Altera

Responsible for Altera India Business as Country Manager, Driving FAEs on demand creation, Driving Channel partners ( distributors ) and other design partners to increase revenue for Altera. Also managing the entire office as India office manager for day to day activities to run the business in India and comply with all government local requirements. He has previously worked for Arrow Electronics. Gangatharan holds an Engineering degree in Electronics and MBA.

Rakesh Agarwal, Country Manager, India & ANZ, Lattice

Rakesh Agarwal heads the India, Australia and New Zealand sales and support at Lattice. In this role, he oversees Lattice’ countrywide sales and support operations which includes field sales personnel, independent manufacturer’s representatives, and distributor partners. He brings more than 10 years of experience to his position, including a variety of posts with leading component distributors prior to joining Lattice. He has extensive knowledge in the PLD industry in India and has been a key contributor to implant PLD's in mainstream applications during its nascent stages in India. Rakesh holds a bachelor's degree in electrical engineering from Pt. RSS University and also holds the postgraduate diploma in VLSI Design.

Mastering FPGA Design through Debug

The single most important feature that one must keep in mind when designing and verifying FPGA based projects is device reconfiguration.  While traditional ASIC RTL design flows require a significant amount of upfront design analysis and verification, an FPGA flow offers a unique dimension of verification - in circuit test and analysis. In this presentation the use of Incremental Design and Debug (IDD) is presented as a technique to accelerate the design and verification of FPGA based RTL.  Various techniques in applying IDD are presented including creating custom in-circuit stimulus drivers as well as in the field methods for further trapping illusive bugs that appear when the FPGA design is at the customer’s site.  At the end of the presentation the several rules of thumb and pointers to further reading are highlighted.  This presentation is intended for novice to experienced users, existing Xilinx based tools and techniques will be shown as well as advanced methods will be presented.

Presenter - Adrian Hernandez, Senior Manager, Xilinx, USA

Adrian Hernández received his B.S.E.E from the University of Texas at El Paso an M.S.E.E. from the University of Colorado. Adrian is a senior manager at Xilinx where he works on ChipScope debug solutions.  Prior to working at Xilinx he worked for ten years at Agilent Technologies (Hewlett-Packard) developing logic analyzer and oscilloscopes solutions with a focus on embedded processors and FPGAs.

Trends and challenges in designing with high speed transceivers based FPGAs, and signal Integrity concerns

FPGAs have now become an essential part of any system design. High speed serial transceivers become very key and must have feature in FPGAs in market segments like Communication, Broadcast, Computer &Storage, Industrial, Medical, Military etc.,  When these high speed serial transceivers getting integrated inside FPGAs, this brings enormous signal integrity and other system integration advantages which enables designers to achieve higher bandwidth, superior system performance, design flexibility, lowering overall system power and at the same time achieving  lower system cost.  If you look at the recent generations of FPGAs available, high speed serial transceivers become default and key part of their offerings.  This session will talk about the trends and challenges of designing with high speed transceivers based FPGAs and signal integrity aspects like SSIO, Pre-emphasis, Receiver equalization and various system serial protocol supports like PCIexpress, 40G/100G Ethernet, Interlaken, CPRI etc.,   then some of the  recent 28nm FPGA trends with high speed serial transceivers going up to 28Gbps performance.

Presenter - John Wei, High Speed System Specialist, Altera Hong Kong

Mr. John Wei joined Altera in January 2005 as high speed technology specialist for Asia Pacific region, focusing on Transceiver and High Speed Protocol application, such as PCI Express, Ethernet, Serial RapidIO and Interlaken etc. Mr. Wei graduated from Beijing University of Aeronautics and Astronautics in 1998 and hold bachelor degree of Electronic Engineering. Prior to joining Altera, John Wei worked in Mindspeed Technology as Senior Field Application Specialist.

Upgrading to SystemVerilog for FPGA Designs

Modern digital designs have to transfer large amount of data across various blocks/IPs especially in the SoC arena. So traditional solutions using scalar or vector variables are too simplistic and do not allow efficient managing of data. Also they can’t enforce directionality among vector fields, can’t capture transfer protocol restrictions, compliance metrics etc. Fortunately, SystemVerilog introduced new construct called 'interface' that wraps data structures, transfer directions, protocol monitors in terms of assertions, cover properties and also compliance metrics via covergroups. The SystemVerilog interface also supports methods of processing the data for TLM style modeling, bandwidth measurement etc. all into one, convenient, new design entity. SystemVerilog interfaces quickly found way into new designs, as they are useful for both RTL designers and Verification engineers.  This tutorial explains typical elements of SystemVerilog interfaces and introduces basic concepts of using them in your designs and testbenches. 

Presentor : Srinivasan Venkataramanan, CTO, CVC

Srinivasan Venkataramanan is a dynamic technical evangelist in the domain of VLSI design, based in Bangalore – India. His areas of interest are the advanced verification solutions and methodologies such as SystemVerilog, OVM, VMM, Assertion-Based Verification, formal verification etc. He is CTO of CVC Pvt. Ltd. Previously he is worked with various design houses, he was actively involved in the verification of leading edge high-speed, multi-million gates ASIC designs. He holds a Masters Degree from the prestigious Indian Institute of Technology (IIT), Delhi in VLSI Design, and Bachelors degree in Electrical engineering from TCE, Madurai.

Memories: interfaces and controllers

The objective of this presentation would be to cover:

• Types of memories:sram, sdram, ddr, ddr2, ddr3
• Evolution of memories and market trend
• Speed/throughput, demystify device jargon
• Memory interfaces, challenges and techniques
• Memory controller operation and integration

Presenter - Sandeep Kulkarni, Apps Manager, Lattice India

Sandeep has worked for various companies such as Memec, Avnet and now with Lattice. He has been associated with FPGAs for a long time & has very deep understanding of various FPGA related technology.

Customer Presentation - RADAR Signal Processing: Case study

As FPGAs increase in density and performance capability,more signal-processing functions like pulse compression, waveform generation, FFTs, matrix-inverse operation etc. can be incorporated in a single FPGA.

Fitting multiple DSP functions into a single FPGA has many integration challenges, but also offers significant advantages in terms of performance and flexibility. Integrating DSP functions into a single FPGA provides system-level reductions in size, weight and power. The place-and-route software now-a-days, have advanced power-awareness features that significantly reduce dynamic power use of the FPGA. Integrating many DSP functions within an FPGA allows for post-design system changes in the signal-processing architecture, whereas using separate DSPs offers complexities like chip interfaces etc once the board is designed. Additional flexibility can be designed into the system by using embedded processors soft/hard core, for data transfer and initial/online settings.

Presenters -

Kaushal Jadia - M. Tech (Communication & Radar), IIT, Delhi, 1997 and BTech (Electrical), Naval College of Engg, 1990 presently heads a team to undertake Signal & Data Processing for ground and ship based surveillance radars. He has previously worked on design of signal processors for sonar systems. In various appointments with the Navy he was involved in induction, maintenance and design of weapons and sensors. Was awarded Lt VK Jain Memorial Gold Medal 2001 for best research effort by a naval officer in the year and Performance Excellence Award 2010, group award for ground based radar projects.

Bhishm Tripathi - obtained his BE (ECE) from CCSU Meerut .Presently he is working in Signal Processing group of LRDE , DRDO. His area of interest is FPGA based RADAR signal processing.

Panel - State of FPGA technology & its adoption in India

Moderator - Dr. Kanwar Jit (KJ) Singh, Chief Architect, Tejas networks

Dr. Kanwar Jit Singh holds a Ph.D. from University of Califoria at Berkeley and was a 1986 Gold Medallist from Indian Institute of Technology at Kanpur during his B.Tech. degree. He worked at Bell Laboratories in the US as Principal Investigator in the area of VLSI Research from 1992 to 2000. He built several groundbreaking VLSI chips, a Single-Chip Color CMOS video camera, a Multi-Processor Digital Signal Processing and an ASIC for multi-dimensional Packet Classification. In 2000, he co-founded Xebeo Communication to develop a core switch  with Layer2, MPLS, and Layer 3 features.  He became Director of VLSI at UTStarcom when it acquired Xebeo Communications in 2003. Dr. Singh relocated to India in 2005 and joined Tejas Networks as  Principal Architect and is deeply involved in the definition and  development of SDH and Ethernet design IP and products based on them.

Panelist 1 - Chidamber Kulkarni, Senior Research Engineer, Xilinx

Chidamber has been working with multi-processors and FPGAs in networking and image processing for more than a decade now. He has been with Xilinx since 2003 and has worked at University of California, Berkeley and IMEC, Belgium in the past. He holds eight US patents, has more than 30 published papers in international conferences and journal. Chidamber has a PhD in EE from Katholieke Universiteit Leuven, Belgium.

Panelist 2 - Rakesh Agarwal, Country Manager, Lattice India

Rakesh Agarwal heads the India, Australia and New Zealand sales and support at Lattice. In this role, he oversees Lattice’ countrywide sales and support operations which includes field sales personnel, independent manufacturer’s representatives, and distributor partners. He brings more than 10 years of experience to his position, including a variety of posts with leading component distributors prior to joining Lattice. He has extensive knowledge in the PLD industry in India and has been a key contributor to implant PLD's in mainstream applications during its nascent stages in India. Rakesh holds a bachelor's degree in electrical engineering from Pt. RSS University and also holds the postgraduate diploma in VLSI Design.

 Panelist 3 - Wai Leng Cheong, Regional Sales Manager, South Asia Pacific, Altera Singapore

Wai-Leng Cheong is the Regional Sales Manager for Altera Corporation, a US$1.3B semiconductor company and a leader in the field of Programmable Logic Devices. Altera provides solutions that include programmable devices, design software, and intellectually property cores to enable customers’ innovation and improves customers’ productivity. Wai-Leng has a broad base knowledge of the electronics business in India, Australia and New Zealand, and ASEAN, and frequently visits customers and partners in these regions.

Panelist 4 - Tarun Gupta, Business Development Manager, National Instruments

Tarun Gupta over seven years of experience in several strategic business responsibilities at National Instruments. As Business Development Manager for the Defense and Telecom segments in India, he has provided expert technical consultancy to reduce costs and increase productivity and reliability of performance critical applications. He also has the expertise of working on several ATE and high channel data aquisition systems like Structural Test Systems for Aircrafts at HAL, HALT for GTRE Engines and Designing Embedded Transceivers on the SDR platform for Ships. He holds an engineering degree in Electrical Engineering from IIT, Kanpur and an MBA from XLRI, Jamshedpur

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